Paper Details

In this rampant age of technology, every new invention and discovery bring some revolutionary changesalong with them. From the era when 3rd generation computers stepped in, then Illiac IV supercomputers and now the7th generation have already hit the market. The basis of all these technologies and the faster processors is the keyingredient – Adders. Adders are one of the most universally accepted components in any digital integrated circuit design.In digital adders, the speed of addition is defined by the time required to propagate carry through the adders.With theadvances in technology, researchers are busy designing adders which offer either high speed, low power consumption orthe combination of both. In this paper, our holistic aim is to optimise the speed of the adders with the minimum timecomplexity and the minimum power utilisation. The design of various adders such as Carry Look Ahead Adder(CLA),Ripple Carry Adder (RCA), Carry Save Adder (CSA), Carry Select Adder(CSL), Carry Skip Adder(CSK), Koggy StoneAdder are discussed and have been compared according to the delay generation and power consumption. Mentionedadders have been designed using Verilog HDL and then simulated and synthesised using Xilinx Vivado v.16 for powerconsumption and delay. In this paper 6 different adders as mentioned above has been implemented and compared interms of speed and power. It has been found that 64 bit Koggy Stone Adder is having minimum delay and minimumpower. (Abstract)

Niharika Mittal, Dr. Shipli Birla, “Design and Implementation of high-speed adders for various digital applications”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 13, pp. -, January 2018.