Area and Power Efficient Layout Design of Inverter
| Author(s) | : | Mehmood-ul –Hasan, Ghulam Ahmad Raza |
| Institution | : | Department of Electronics & Communication Engineering,Baba Ghulam Shah Badshah University, Rajouri |
| Published In | : | Vol. 5, Issue 13 — January 2018 |
| Page No. | : | - |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
In recent years, the demand for low power devices has grown significantly. This growth is mainly due to the fastgrowth of battery-operated semiconductor devices such as cell phone, tablets, laptop etc. Reducing power consumption andsurface area in integrated circuit is an important factor for both portable and desktop applications. In this paper an inverterand its layout have been designed using PMOS and NMOS transistors. The result has been compared in terms of powerconsumption and surface area. The simulated results show that semi-custom layout of an inverter consumes 52.5% morepower and 35.9% more surface area than the full custom layout of inverter
Mehmood-ul –Hasan, Ghulam Ahmad Raza, “Area and Power Efficient Layout Design of Inverter”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 13, pp. -, January 2018.
