📄 IJAERD-OJS-6286
A NOVEL APPROACH FOR VERIFICATION OF RISC-V PROCESSOR
| Author(s) | : | Ramanpreet Virdi, Neeraj Kr. Shukla |
| Institution | : | Department of Electrical, Electronics & Communication Engineering, The NorthCap University, Gurgaon, Haryana, India |
| Published In | : | Vol. 5, Issue 13 — January 2018 |
| Page No. | : | - |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Abstract
The CPU is a standout amongst the most significant segments of our PCs, dependable of performingessential figuring, legitimate correlations and moving information around. These straightforward errands are thebuilding squares of any more unpredictable operation, and make running our frameworks and projects conceivable. Thispaper shows the better approach to verify the RISC-V (Reduced Instruction Set Architecture) processor which can inciteminimal effort as the open source Verification Language (Vlang).
🕮 How to Cite
Ramanpreet Virdi, Neeraj Kr. Shukla, “A NOVEL APPROACH FOR VERIFICATION OF RISC-V PROCESSOR”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 13, pp. -, January 2018.
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