Design of Efficient Binary Comparatorsin Quantum-Dot Cellular Automata
| Author(s) | : | M.HARI CHANDRA REDDY, L.S.DEVARAJ |
| Institution | : | PG Scholar, VLSI System Design, Intellectual Institute of Technology, AP, India |
| Published In | : | Vol. 2, Issue 9 — September 2015 |
| Page No. | : | 45-72 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultradense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmeticcircuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still posesseveral challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a newdesign approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equationsrequired to perform the comparison function are proposed. The new strategy has been exploited in the design of two differentcomparator architectures and for several operands word lengths. With respect to existing counterparts, the comparatorsproposed here exhibit significantly higher speed and reduced overall area.
M.HARI CHANDRA REDDY, L.S.DEVARAJ, “Design of Efficient Binary Comparatorsin Quantum-Dot Cellular Automata”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 9, pp. 45-72, September 2015.
