Paper Details

Digital arithmetic operations are the most important in the design of Digital Signal Processing (DSP) andApplication Specific Integrated Circuit (ASIC) systems. Addition and Multiplication are the most basic arithmeticoperations. Floating point (FP) multiplication is widely used in large set of scientific and signal processing computation.The speed of floating point arithmetic unit is very crucial performance parameter which impinges the operation of thesystem. A fast and accurate operation of a digital system is greatly influenced by the performance of different adders andmultipliers using different methodology. Emerging trends in low power made attention towards the search of low power,high speed and area efficient adders and multipliers architecture. In this project, single precision (32-bit) floating pointmultiplier is designed. The main focus of this design is to reduce area, power and path delay to enhance the speed of themultiplication and addition operation. For floating point multiplier, Booth recoded multiplier is used where it reducesthe number of partial products and thereby increase the speed of multiplication of the mantissa bits. For partial productsaddition, Carry Look-Ahead adder (CLA) and Kogge-Stone Adder (KSA) is implemented separately. The area, delay,power, speed, Power Delay Product (PDP) and Energy Delay Product (EDP) of two different implementation results arecompared. Xilinx and ModelSim tool is used for simulation and VHDL coding for the design.

R Kalaimathi, R Senthil Ganesh, “Design of High Speed, Low Power and Area Efficient 32-Bit Floating Point Multiplier”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 11, pp. 1164-1171, November 2017.