Paper Details

All digital systems need to synchronize between Integrated Circuits and functional blocks, mainly toprogress digital systems operations for excellence in performance. Future processors need to work with different ICs andIPs, whose operating speed is different; there is requirement for high speed clocks. This has to be done by just using thelow frequency on board clock. To generate the on-chip clocks to have well-timed, Phase locked-loops (PLLs) are used.But designing a fully digital PLL is needed because all the designs are digital and analog component will need morepower and will reduce efficiency. Most of the traditional PLL are monolithic design with other circuits. The proposedDPLL is just based on counters, dividers and digital phase lock detectors which are easy to fabricate when compared toanalog component and can be integrated in any system easily. It can generate wide range of frequencies and has in builtBIST to test the operation of PLL and to determine characteristics like lock time, jitter and duty cycle. The experimentalresults of DPLL with waveforms are shown for 50 MHz reference clock signal to generate 200 MHz clock DPLL. BISTfor the PLL is implemented using TESSENT TOOL.

PANCHETI HAREESH, SIMHADRI VENKATA ABHISHEK, “Design of DPLL and Implementation of BIST to Evaluate its Characteristics”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 11, pp. 122-128, November 2017.