Paper Details

This work is based on design of low power PLL with the help of CSVCO. The conventional voltage controloscillator will take more power as compare to CSVCO. VCO is the major part of PLL circuit and it affects the systemperformance in terms of power consumption and noise performance. In modern VCO design power consumption andhigh output frequency range have become important performance metrics .To design PLL proposed circuit will replacePLL with CSVCO .Because the VDD varies ±10% of 1.8V i.e from 1.62V to 1.98V.For this voltage variation the ringarchitecture produces an output frequency from 4.175GHz to 5.077GHz with the difference of 992 MHz, which is largevariation. The output frequency is not stable when it is dependent on VDD. In most of the application PLL are used forclock and data recovery purpose to achieve this the CSVCO will use. This CSVCO is applicable for PLL application suchas clock generation and recovery, frequency synthesizer, fast locking in digital circuit etc. The proposed circuit area andpower consumption are very less and compatible for PLL application. The circuit analysis is performed and respectivewave form are generated at 1MHz and power gain estimation at1GHz is 33.22E-6 is obtained with supply voltage of 1V.All the generated wave form are analyzed by using Cadence Virtuoso Gpdk045nm CMOS technology.

Jagbandhan Kindo, K.. Bapayya, “Design of Low Power Phase Locked Loop using Current Starved Voltage Controlled Oscillator”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 10, pp. 54-60, October 2017.