COMPARATIVE PERFORMANCE ANALYSIS OF OPTIMIZED POWER AND AREA FOR FULL ADDER USING GDI CELL
| Author(s) | : | NANDEESH M, PRADEEP N T, SAGAR H D, SUNIL H S, VINAY KUMAR B S |
| Institution | : | Assistant Professor Dept of ECE BGSIT BG Nagar |
| Published In | : | Vol. 5, Issue 5 — May 2018 |
| Page No. | : | 81-89 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
This paper presents a high drivability of full adder with less area and power consumption. This GDI basedfull adder is implemented by using both gate diffusion input (GDI) technique and pass transistor logic that leads to be areduced area and power.. The comparison has been done between existing systems like CMOS, CPL, 14T full adder andproposed full adder. All full adders are designed with 0.18um in tanner schematic and simulations are done in T-Spice.Tool .By Using this full adder we have designed the ripple carry adder and carry skip adder which is compared with allexisting systems and finally concluded that our proposed method is showing better results in terms of area and powerhence we can say our method is efficient in area and power consumption.
NANDEESH M, PRADEEP N T, SAGAR H D, SUNIL H S, VINAY KUMAR B S, “COMPARATIVE PERFORMANCE ANALYSIS OF OPTIMIZED POWER AND AREA FOR FULL ADDER USING GDI CELL”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 5, pp. 81-89, May 2018.
