REA OPTIMIZATION AND PERFORMANCE IMPROVEMENT OF CARRY SPECULATIVE ADDITION BY MODIFYING BLOCK ADDER AND ERROR CORRECTION CIRCUIT
| Author(s) | : | V.Chiranjeevi Siva Prasad, R.T.V.RamTeja, P.SaiSowmyaSree, U.Pradeep |
| Institution | : | Department of Electronics and Communication Engineering, Bapatla Engineering College P.P.M.Prasad, Asst. professor Dept. of Electronics and Communication Engineering, Bapatla Engineering College |
| Published In | : | Vol. 5, Issue 3 — March 2018 |
| Page No. | : | 888-895 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
This paper proposes carry speculative addition using modified error correction, block adder design to reducecritical path delay there by reducing area and power consumption. The modified error correction block and block adderpossesses less number of gates compared with existing circuit. The complete proposed Carry Speculative Addition usingmodified error correction and block adder with a data latching circuit to get continuous data into circuit architecture isimplemented using Verilog HDL and the design is simulated using Xilinx ISE and vivado 2016.4,artix 7 family deviceXC7A100TCSG324-1.
V.Chiranjeevi Siva Prasad, R.T.V.RamTeja, P.SaiSowmyaSree, U.Pradeep, “REA OPTIMIZATION AND PERFORMANCE IMPROVEMENT OF CARRY SPECULATIVE ADDITION BY MODIFYING BLOCK ADDER AND ERROR CORRECTION CIRCUIT”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 5, Issue 3, pp. 888-895, March 2018.
