DESIGN OF REDUCED POWER CONSUMPTION IN LOW VOLTAGE DROPOUT REGULATOR
| Author(s) | : | Miss. Shivani .S. Tantarpale, Prof. Ms. Archana O. Vyas |
| Institution | : | (Electronics & Telecommunication Dept.,G. H. Raisoni college of engineering & Management.Amravati, India) |
| Published In | : | Vol. 3, Issue 12 — December 2016 |
| Page No. | : | 268-272 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
A low-dropout or LDO regulator is a linear DC voltage regulator which can govern the output voltage evenwhen the stock voltage is very adjacent to the output voltage. The recompenses of a low dropout voltage regulatorinclude the nonexistence of switching noise ( as no switching takes place), minor device size ( as neither large inductorsnor transformers are needed), and larger design easiness (usually comprises of a reference, an amplifier and a passelement). A noteworthy adiabatic logic with 90 nm CMOS technology is proposed to reduce influence of power supplyreductions well as a simple symmetric operational trance-conductance amplifier is used as the error amplifier (EA), witha current division method used to enhance the gain and also mend the bandwidth of the LDO regulator.
Miss. Shivani .S. Tantarpale, Prof. Ms. Archana O. Vyas, “DESIGN OF REDUCED POWER CONSUMPTION IN LOW VOLTAGE DROPOUT REGULATOR”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 3, Issue 12, pp. 268-272, December 2016.
