SYSTEMATIC ERROR CODES IMPLIMENTATION FOR MATCHED DATA ENCODED
| Author(s) | : | B.YSAWANTH KUMAR, L.S.DEVARAJ |
| Institution | : | PG Scholar, VLSI System Design, Intellectual Institute Of Technology, AP, India |
| Published In | : | Vol. 2, Issue 9 — September 2015 |
| Page No. | : | 104-109 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
In current scenario, there are situations in a computing system where incoming information needs to becompared with a piece of stored data to locate the matching entry, e.g., cache tag array lookup and translation look-asidebuffer matching. In this paper, a new architecture to reduce complexity and latency for matching the data protected with anerror-correcting code (ECC).It is based on the fact that the code word of an ECC generated by encoding is usuallyrepresented in a systematic form, and it consists of the raw data and the parity informa tion. The proposed architectureparallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, inaddition, a modified butterfly formed weight accumulator (BWA) is proposed for the effic ient computation of the Hammingdistance. The proposed architecture examines whether the incoming data matches the sto red data if a certain number oferroneous bits are correct.
B.YSAWANTH KUMAR, L.S.DEVARAJ, “SYSTEMATIC ERROR CODES IMPLIMENTATION FOR MATCHED DATA ENCODED”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 9, pp. 104-109, September 2015.
