📄 IJAERD-OJS-0787
All Digital Phase Locked Loop with High DCO resolution
| Author(s) | : | Kunjal Parmar, Kirit Patel, Alpesh Patel |
| Institution | : | Vishwakarma Government Engineering College, Chandkheda, Ahmedabad |
| Published In | : | Vol. 2, Issue 5 — May 2015 |
| Page No. | : | 160-164 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Abstract
In this paper we propose a very high-resolution all digital phase locked loop (ADPLL). ADPLL is designed withthe cell library and described in hardware description language (HDL). We design a digital controlled oscillator with 1.06ps resolution for phase frequency detector minimized up to 5ps. So this ADPLL is suitable for system on chip application.
🕮 How to Cite
Kunjal Parmar, Kirit Patel, Alpesh Patel, “All Digital Phase Locked Loop with High DCO resolution”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 5, pp. 160-164, May 2015.
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