IMPLEMENTATION OF 2GBPS CLOCK AND DATA RECOVERY CIRCUIT USING PLL WITH HIGH JITTER TOLERANCE
| Author(s) | : | Dr. Suma M.S., Krishna Basidoni |
| Institution | : | Electronics and communication (VLSI Design), R.V.COLLEGE OF ENGG. AND TECH, BANGALORE |
| Published In | : | Vol. 2, Issue 2 — February 2015 |
| Page No. | : | 56-63 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
The data integrity that the SerDes offers is predominantly due to the Clock and Data Recovery Circuit (CDR)employed within the design. The CDR takes the incoming data and generates a clock using the data specs which can then beused by the deserializer to sample the data accurately. This paper looks into the basic principles of operation of PhaseLocked Loops, Clock and Data recovery circuits and their building blocks for a 2 Gbps SerDes link with high jitter tolerance.Implementation of differential mode VCO with low gain to reduce the jitter. It summarizes the challenges in design and alsopresents a Cadence approach to the circuit design in 180 nm CMOS technology.
Dr. Suma M.S., Krishna Basidoni, “IMPLEMENTATION OF 2GBPS CLOCK AND DATA RECOVERY CIRCUIT USING PLL WITH HIGH JITTER TOLERANCE”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 2, pp. 56-63, February 2015.
