Characterization and Simulation of High Speed CMOS Operational Amplifier Using Split-length Compensation
| Author(s) | : | Rahul Chaudhari, Rajnikant Soni |
| Institution | : | PG Student, Gujarat Technology University, Electronics and Communication, LCIT-Bhandu, Mehsana, Gujarat, India,rahul.lcit@yahoo.com |
| Published In | : | Vol. 1, Issue 5 — May 2014 |
| Page No. | : | 765-773 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
An analytical design guide was formulation for the design of 3-stage CMOS Op-Ampwith the Split-length Compensation. The proposed design guide generates straight-forwardly thedesign parameters such as W/L ratio and current of each transistor from the given specification, suchas, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. TheOPAMP is designed to exhibit a unity gain frequency of 1.25GHz and exhibits a gain of 79.87dBwith an 89.68 phase margin. Design has been carried out in Mentor graphics tools.The results arecompared with respect to standard characteristics of the op-amp with the help of graph and table.Simulation results agree with theoretical predictions. Simulations confirm that the settling time canbe further improved by increasing the value of GBW; the settling time is achieved 49ns. It has beendemonstrated that when W/L increases the parameters GBW increases and settling time reduces sothe speed of Op-Amp is high.
Rahul Chaudhari, Rajnikant Soni, “Characterization and Simulation of High Speed CMOS Operational Amplifier Using Split-length Compensation”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 5, pp. 765-773, May 2014.
