NON OVERLAPPING CLOCKS FOR SWITCHED CAPACITOR CIRCUITS
| Author(s) | : | Dhaval V. Agrawal, Mehul L. Patel |
| Institution | : | Research Scholar EC Dept., L. C. Institute of Technology, Bhandu, Gujarat Technological University, Ahmedabad, India |
| Published In | : | Vol. 1, Issue 5 — May 2014 |
| Page No. | : | 311-315 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Switched capacitor techniques are very popular forimplementation of Mixed Signalblocks in CMOS VLSI. Non-OverlappingClock (NOC) generator is one of the key blocksin theimplementation of switched capacitor circuits. StandardNOC generator circuits available in theliterature uses delaycircuits realized using simple inverters connected in a chain. By usinginverter chain delay generated is very small so to generate larger delay it requires larger numbersof inverters. This affects the area and powerbudget of the design. In this work it is proposed touse invertersin inverted form to realize significant delay with less number oftransistors.Simulation results suggest that the proposed circuitwill be area and power efficient as comparedto the conventionalNOC circuits
Dhaval V. Agrawal, Mehul L. Patel, “NON OVERLAPPING CLOCKS FOR SWITCHED CAPACITOR CIRCUITS”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 5, pp. 311-315, May 2014.
