Low Power Folding and Interpolating Analog to Digital Converter using 180nm Technology
| Author(s) | : | Jayesh L. Prajapati, Prof. Priyesh P. Gandhi |
| Institution | : | M.E. Student, Department of Electronics & Communication Engineering,Laljibhai Chaturbhai Institute of Technology, Bhandu-38412, Indiaprajapatijayesh02@gmail.com |
| Published In | : | Vol. 1, Issue 5 â May 2014 |
| Page No. | : | 285-294 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Folding and interpolating A/D converters have been shown to be an effective means ofdigitization of high bandwidth signals at intermediate resolution. The paper focuses on design of 5-bitfolding & interpolating ADC. The converter architecture is designed with reduced number ofcomparators and minimum hardware. The folding amplifier with folding factor=4 can be used toproduce more than one zero-crossing point to reduce required number of comparators. To achieve thedesign goal, folding amplifier is used in the design of coarse and fine converter both. To reduce thepower consumption, encoder based on XOR-OR logic is used. The design is implemented using0.18Ξm technology at 1.8Vsupply voltage.
Jayesh L. Prajapati, Prof. Priyesh P. Gandhi, “Low Power Folding and Interpolating Analog to Digital Converter using 180nm Technology”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 5, pp. 285-294, May 2014.
