High Speed CMOS Charge Pump Circuit for PLL Applications Using 180nm CMOS Technology
| Author(s) | : | Ronak J. Patel, Shaishav P. Patel, Nilesh D. Patel |
| Institution | : | PG Student, CSPIT, Changa |
| Published In | : | Vol. 1, Issue 5 — May 2014 |
| Page No. | : | 441-445 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
The performance of charge pumps depends heavily on the ability to efficientlygenerate high voltages on-chip while meeting stringent power and area requirements. Thepaper presents a High Speed CMOS charge pump circuit for PLL applications using 180nmCMOS technology. The proposed circuit has simple symmetric structure and provides morestable operation while reducing spurious jump phenomenon. The output voltage of presenteddesign can be increased up to 1000mV. The functionality of charge pump has been tested atoperating based frequency of 1000 MHz.
Ronak J. Patel, Shaishav P. Patel, Nilesh D. Patel, “High Speed CMOS Charge Pump Circuit for PLL Applications Using 180nm CMOS Technology”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 5, pp. 441-445, May 2014.
