Survey: Design Procedure of VLSI, FPGA & ASIC Life Cycle’s
| Author(s) | : | M.Pranavi Reddy, M.Harshitha, Ch.Revathi, T. Subha Sri Lakshmi |
| Institution | : | Mtech Student, VLSI System Design, CVR College of engineering, Hyderabad, India |
| Published In | : | Vol. 4, Issue 11 — November 2017 |
| Page No. | : | 1083-1091 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
In real time world VLSI plays a prominent role. The paper presents a survey of VLSI, FPGA & ASIC lifecycles and its design procedure. The present portable electronic devices like smart phones, Laptops etc., are capable ofmulti-functional and multi domain application areas. These types of applications are possible due to the IntegratedCircuit (IC) technology and changes in the design takes place in terms of reduction in transistor size, supply voltage,time to market etc. These types of complex system on Chip (Soc) devices are designed by using Electronic DesignAutomation (EDA) tools to meet all nonfunctional IC design constraints. The selection of EDA tool is based on the typeof design analysis, IC design flow, designer domain knowledge, nonfunctional optimization constraints etc. This papergives an overview of VLSI, FPGA & ASIC design flow, advantages, applications and few manufacturing companies ofFPGA and ASIC.
M.Pranavi Reddy, M.Harshitha, Ch.Revathi, T. Subha Sri Lakshmi, “Survey: Design Procedure of VLSI, FPGA & ASIC Life Cycle’s”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 11, pp. 1083-1091, November 2017.
