FPGA IMPLEMENTATION OF ENCODER and DECODER FOR GOLAY CODES
| Author(s) | : | G.SHANTHI, Dr.K.SRINIVAS RAO, S.SRILEKHA |
| Institution | : | Research Scholar, Dept. of ECE, KL University & Assitant Professor, Dept. of ECE ,VNRVJIET, Hyderabad, T.S, India |
| Published In | : | Vol. 4, Issue 11 — November 2017 |
| Page No. | : | 1015-1020 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
This brief lays out FPGA implementation of encoder and decoder for Golay codes. Golay codes are errordetection and correction codes and it corrects errors in the receiving end in the received data to reduce retransmissionevents . Encoding algorithm for both the binary Golay code(G23) and extended binary Golay code (G24)implementation based on cyclic redundancy check encoding method. Decoding architecture for G24(24, 12, 8) based onan error detection and correction method and here correction upto four erros is possible in the data. Synthesis andSimulation results obtained in Xilinx tool. Debugging FPGA design using XILINX Chipscope Pro tool
G.SHANTHI, Dr.K.SRINIVAS RAO, S.SRILEKHA, “FPGA IMPLEMENTATION OF ENCODER and DECODER FOR GOLAY CODES”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 11, pp. 1015-1020, November 2017.
