Design and comparison of Low Power 64-Bit ALU using CMOS and Transmission Gate Logic
| Author(s) | : | Mangali Amarnath, Sridhar Cherala |
| Institution | : | M Tech VLSI System Design Dept. of Electronic & Communication Engineering, CVR College Of Engineering, Hyderabad |
| Published In | : | Vol. 4, Issue 10 — October 2017 |
| Page No. | : | 126-134 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Arithmetic and logical unit (ALU) is an important block of microprocessor. Now days for most of theapplications of digital circuits the important attributes are minimizing power consumption and area whreas maximizingspeed. The main aim of this project is to design 64 bit ALU with less number of transistors using fast complementarymetal oxide semiconductor logic and Transmission gate logic. The Arithmetic and Logical Unit (ALU) is designed toperform all the Arithmetical and Logical operations, including bit shifting operation which is needed to be done foralmost any data that is being processed by the Central Processing Unit (CPU). The proposed 64 bit ALU is designedand simulated in Cadence Virtuoso Tools in GPDK 45nm Technology
Mangali Amarnath, Sridhar Cherala, “Design and comparison of Low Power 64-Bit ALU using CMOS and Transmission Gate Logic”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 10, pp. 126-134, October 2017.
