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📢 Call for Papers — Volume 13, Issue 5 (May 2026) | Submission Deadline: May 31, 2026 | Rapid peer review: 2–3 days | Impact Factor: 7.37 (SJIF 2026)

Paper Details

📄 IJAERD-OJS-3568

Design of 5-bit Flash ADC through Domino Logic in 180nm, 90nm, and 45nm Technology

Author(s):V. komali, G. Balaraju
Institution:Student, Dept of ECE, CVR college of Engineering, Hyderabad, India
Published In:Vol. 4, Issue 8 — August 2017
Page No.:713-718
Domain:Engineering
Type:Research Paper
ISSN (Online):2348-4470
ISSN (Print):2348-6406
Abstract

In this paper high speed 5-bit Flash analog to digital converter (ADC) through Domino logic is designed in180nm, 90nm, and 45nm CMOS technology with sampling rate of 4GS/s. Domino logic allows rail to rail logic swing. Itwas developed to speed up the circuit. The physical circuit is more compact than previous design compare to power anddelay. This can be used for high speed applications. Flash analog to digital converter is ideal for applications requiringvery large bandwidth, but they consume more power than other ADC architectures and are generally limited to 8-bitresolution.

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🕮 How to Cite

V. komali, G. Balaraju, “Design of 5-bit Flash ADC through Domino Logic in 180nm, 90nm, and 45nm Technology”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 8, pp. 713-718, August 2017.

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Vol. 13 | Issue 5
May 2026