Paper Details

Multiplier is the key element in the digital and high performance systems such as FIR filters, digitalprocessors and microprocessors etc. Most of the arithmetic operations are done using multipliers. Designing multipliersfor the high –speed integrated circuit with low power consumption is today’s major concern for the VLSI field. Amongthe existing multiplier, Wallace tree multiplier is popular multiplier architecture. Wallace tree multiplier is a parallelmultiplier, hence faster than an array multiplier. Speed of conventional Wallace tree multiplier can be further improvedby using compressors. The target is achieved by making use of 4:2, 5:2, and 6:2 compressor techniques. In this paper,two numbers of 8-bits each are multiplied using Wallace tree multiplier. Comparison is done between Wallace treecompressors incorporating 10 T full adders and 28 T full adders. Performance analysis is in terms of power, delay andpower-delay product. The multiplier was implemented at the circuit level in 45nm CMOS technology Cadence Virtuosotool.

NIKITA SINGH, “Design of Low power & High Speed 8-Bit Wallace Tree Multiplier using 10T Full-adder”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 8, pp. 655-661, August 2017.