A FAST FPGA DEVELOPMENT OF RSD BASED ECC PROCESSOR
| Author(s) | : | P HARI GURU PRASAD, Ms D. SRILATHA |
| Institution | : | PG Scholar, Dept of ECE, VLSI-D, Sri Venkateswara College of Engineering, Tirupathi, Andhra Pradesh, India |
| Published In | : | Vol. 4, Issue 8 — August 2017 |
| Page No. | : | 336-346 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
In this paper, an exportable application-particular education-set elliptic curve cryptography processorprimarily based on redundant signed digit illustration is proposed. The processor employs extensive pipelining strategies forKaratsuba–Of man approach to obtain excessive throughput multiplication. Furthermore, an green modular adder withoutcontrast and a excessive throughput modular divider, which results in a brief facts path for maximized frequency, are carriedout. The processor supports the advocated NIST curve P256 and is based on an prolonged NIST discount scheme. Theproposed processor performs single point multiplication using points in affine coordinates in 2.26 ms and runs at a maximumfrequency of one hundred sixty MHz in Xilinx Virtex 5 (XC5VLX110T) area-programmable gate array.
P HARI GURU PRASAD, Ms D. SRILATHA, “A FAST FPGA DEVELOPMENT OF RSD BASED ECC PROCESSOR”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 8, pp. 336-346, August 2017.
