Paper Details

The computational complexity of various data processing applications is vastly reduced when signals arerepresented in the frequency domain. In launch vehicle systems, FFT is required for telemetry data processingapplications. Since the systems work in real time, a fast and efficient computation of the FFT is called for. FFTmultiplication deals with Floating point numbers. Vedic mathematics is an ancient multiplication procedure which iswidely used in every field that requires computations. The Urdhva Tiryakbhyam sutra is used because it will reducecomputation time than conventional multipliers. Digital Signal Processing applications essentially require themultiplication of binary floating point numbers. For IEEE754 floating point multiplier implementation, VedicMultiplication Method is used. The ease of multiplication of Mantissa part is done by Urdhva Tiryakbhyam method. Thispaper deals with the 24 bit floating point implementation using IEEE754 multiplication based on vedic mathematics andcompare the result with conventional multi plier. Design and HDL coding was carried out using Verilog using the LiberoIdeV9.1 project environment, natively used for the Actel Pro-Asic devices. The code synthesis was done using Synplifyand simulation stage was done using Modelsim

Athira Menon M S, Renjith R J, “IMPLEMENTATION OF 24 BIT HIGH SPEED FLOATING POINT VEDIC MULTIPLIER”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 4, Issue 5, pp. 742-749, May 2017.