DESIGN OF A LOW POWER HIGH SPEED DYNAMIC DOUBLE-TAIL COMPARATOR
| Author(s) | : | G. Suresh, V. Siva Reddy |
| Institution | : | ECE, VR Siddhartha engineering college |
| Published In | : | Vol. 3, Issue 8 — August 2016 |
| Page No. | : | 114-120 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Comparator is a major building block of analog to digital converter (ADC) since speed of ADC is determined bythe comparator.The need for ultra-low-power, area efficient and high speed analog-to-digital converters is pushing towardthe use of dynamic regenerative comparators to improve speed and efficiency of power.In this discuss on high speed, lowpower & low-voltage consumption comparators such as dynamic comparator,dynamic double-tail comparator and modifieddouble tail comparators are studied. Based on results a new double tail comparator is proposed and compared to dynamiccomparator, dynamic double-tail comparator and modified double-tail comparator in terms of delay and power. So thatpower consumption and delay time are significantly reduced even in small supply voltage. The simulation results will beshown in Mentor Graphics 130nm technology
G. Suresh, V. Siva Reddy, “DESIGN OF A LOW POWER HIGH SPEED DYNAMIC DOUBLE-TAIL COMPARATOR”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 3, Issue 8, pp. 114-120, August 2016.
