POWER OPTIMIZATION AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES
| Author(s) | : | K. Sarada kiranmayi, T. Raja Sekhar |
| Institution | : | M. Tech student, VR Siddhartha engineering college, Vijayawada |
| Published In | : | Vol. 3, Issue 8 — August 2016 |
| Page No. | : | 107-113 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
The area and power consumption are reduced by replacing flip-flops with pulsed latches. The flip-flopperformance is a significant element to regulate the efficiency of the entire synchronous circuit. The replacing method slovestiming problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals in conventionalsingle pulsed clock signal. The pulsed clock signals uses a small number of shift registers by grouping many sub shifterregisters and using additional temporary storage latches. In addition, we further proposed a modified sub-shift registerusing pulsed latches and 512-bit shift register to reduce the power.
K. Sarada kiranmayi, T. Raja Sekhar, “POWER OPTIMIZATION AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 3, Issue 8, pp. 107-113, August 2016.
