Sophisticated design of low power high speed full adder by using SR-CPL and Transmission Gate logic
| Author(s) | : | Patthan Rahamath Nawaz, M.Kalpana Bai |
| Institution | : | P.G Student in VLSI, Department of E.C.E,IITA, Anantapuramu |
| Published In | : | Vol. 2, Issue 3 — March 2015 |
| Page No. | : | 137-142 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
Adder are the basic building blocks of any computing system.. These Arithmetic operations are widely used in mostdigital computer systems. Addition will be the basic component in arithmetic operation and is the base for arithmeticoperations such as multiplication and the basic adder cell can be modified to function as subtractor by adding another xorgate and can be used for division. Therefore, 1 -bit Full Adder cell is the most important and basic block of an arithmetic unitof a system. In this paper we analysis the 1-bit full adder using SR-CPL style of full adder design and Transmission gate styleof design
Patthan Rahamath Nawaz, M.Kalpana Bai, “Sophisticated design of low power high speed full adder by using SR-CPL and Transmission Gate logic”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 2, Issue 3, pp. 137-142, March 2015.
