Comparative Analysis of Full Adders Using different MOS Technologies
| Author(s) | : | Yadwinder Kaur, Sonia Malhotra |
| Institution | : | |
| Published In | : | Vol. 1, Issue 8 — August 2014 |
| Page No. | : | 145-149 |
| Domain | : | Engineering |
| Type | : | Research Paper |
| ISSN (Online) | : | 2348-4470 |
| ISSN (Print) | : | 2348-6406 |
With the development in the fabrication techniques the numbers of the transistors on a chip are increasing at muchfaster rate, results in the very large scale integration. This paper discusses the comparative analysis of full adder circuits interms of higher speed and size. All these three parameters depend upon each other and trade-off exists within these. A 4bitadder is designed using different MOS technologies These Techniques include CMOS technology designing with transmissiongate and designing adder with combination of Complimentary Pass Logic and Transmission gate & simulated using 180nm,130nm & 100nm technology files
Yadwinder Kaur, Sonia Malhotra, “Comparative Analysis of Full Adders Using different MOS Technologies”, International Journal of Advance Engineering and Research Development (IJAERD), Vol. 1, Issue 8, pp. 145-149, August 2014.
